以多層次網格為基礎之晶片網路設計

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Please use this identifier to cite or link to this item: http://140.128.103.80:8080/handle/310901/19950

Title:	以多層次網格為基礎之晶片網路設計
Other Titles:	Network-on-Chip Design Based on Multi-level Mesh
Authors:	蘇柏豪 Bo-Hao Su
Contributors:	蔡坤霖 Kun-Lin Tsai 東海大學電機工程學系
Keywords:	系統單晶片;晶片網路;二維網格;路由器設計 System-on-Chip ( SoC );Network-on-Chip( NoC );mesh;router design
Date:	2012
Issue Date:	2013-01-02T02:33:12Z (UTC)
Abstract:	隨著製程及設計技術的快速進步，系統單晶片的使用日益廣泛。系統單晶片可含有數量龐大的矽智財(Silicon IP; SIP)模組，這些系智財模組在傳統的SoC中使用匯流排(bus)負責內部通訊傳輸。然而，在匯流排傳輸模式下，傳輸資料延遲、電路同步、雜訊和功率消耗的問題，均隨著製程縮小而需要大幅度改進。另一方面，當單一晶片內可擺放電晶體總數量急遽增加而愈來愈複雜時，晶片內部的通訊傳輸將影響晶片處理效率，傳統的匯流排傳輸已經漸漸地不敷使用。因此，為了確保各個模組之間資料傳輸與訊號溝通的正確性，網路封包傳輸概念被應用於晶片上，以進行不同矽智財模組間的資料交換。這種將單晶片系統內部的傳輸介面轉換成由網路模式傳輸的方式，稱為晶片網路(Network-on-Chip; NoC)設計。晶片網路具有良好的擴充性及較為可靠的晶片通訊方式。二維網格(2D mesh)拓樸架構在過去的晶片網路設計中被普遍地使用，因為它能使用簡單的路由演算法，並且具有好的擴充性。但是由於二維網格拓樸有相對較大的網路半徑，造成有些長距離的封包傳送有較大的傳輸延遲。因此在這篇論文中我們針對傳統網格拓樸提出一個多層次的設計方法，主要的概念是讓長距離資料傳送可以利用另一層網格拓樸進行快速傳輸。實驗結果顯示，我們所提出來的多層次網格架構在電路面積增加20%的情況下，可以節省50%功率消耗，並改善70%效能，我們所提出來的方式確實可行。關鍵字：系統單晶片、晶片網路、二維網格、路由器設計、矽智財 With the rapid progress of design technology, the use of SoC is increasingly widespread. SoC contains a huge number of Silicon IP (SIP) modules, and the SIP modules often use on-chip buses to transmit the data or control signals. However, the problems of communication latency, circuit synchronization, signal noise and power consumption need to be improved due to narrowing process. To ensure the accuracy of data communication between each module, the network packet transmission concept is applied to on-chip communication, which is called Network-on-Chip (NoC) design. NoC is a flexible and reliable on-chip communication architecture. 2D mesh topology is often used for NoC design, because it can use a simple routing algorithm, and has good scalability. However, the 2D mesh topology has relatively large radius of the network, and causes larger transmission delay for long distance packets. In this paper, we propose an improved design for 2D mesh topology. The main concept is long distance data transmission take another layer of mesh to achieve fast communication goal. The experimental results show that the multi-level mesh architecture can save 50% power, and improve 70% performance with 20% area increase.Keyword：System-on-Chip ( SoC ), Network-on-Chip( NoC ), mesh, router design, Silicon IP (SIP)
Appears in Collections:	[電機工程學系所] 碩士論文

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