Millisecond anneal and short-channel effect control in Si CMOS transistor performance

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題名:	Millisecond anneal and short-channel effect control in Si CMOS transistor performance
作者:	Nieh, C.F.,?Ku, K.C.?,?Chen, C.H.,?Chang, H.,?Wang, L.T.,?Huang, L.P.,?Sheu, Y.M.,?Wang, C.C.,?Lee, T.L.,?Chen, S.C.,?Liang, M.S.,?Gong, J.
貢獻者:	Department of Electrical Engineering, Tunghai University
關鍵詞:	Annealing;Short-channel effect (SCE);Ultrashallow junction (USJ)
日期:	2006
上傳時間:	2013-05-15T09:04:52Z (UTC)
摘要:	In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ∼18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology. ? 2006 IEEE.
關聯:	IEEE Electron Device Letters 27 (12) , pp. 969-971
顯示於類別:	[電機工程學系所] 會議論文

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