Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications

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Title:	Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications
Authors:	Hu, C.-M., Hung, C.-Y., Chu, C.-H., Chang, D.-C., Juang, Y.-Z., Gong, J., Huang, C.-F., Chin, C.-M.
Contributors:	Department of Electrical Engineering, Tunghai University
Keywords:	Antifuse;Charge-trapping;EEPROM;Mask ROM;Non-overlapped implantation
Date:	2012
Issue Date:	2013-05-15T09:06:00Z (UTC)
Abstract:	Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 10 9 and a program speed as high as 1 μs. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions.? 2011 Elsevier Ltd. All rights reserved.
Relation:	Microwave and Optical Technology Letters 54 (2) , pp. 329-332
Appears in Collections:	[電機工程學系所] 期刊論文

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