Modeling and verification of real-time embedded systems with urgency

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題名:	Modeling and verification of real-time embedded systems with urgency
作者:	Hsiung, P.-A., Lin, S.-W., Chen, Y.-R., Huang, C.-H., Shih, C., Chu, W.C.
貢獻者:	Dept. of Computer Science, Tunghai University,
關鍵詞:	Formal verification;Modeling;Urgency
日期:	2009
上傳時間:	2013-05-15T09:06:17Z (UTC)
摘要:	Real-time embedded systems are often designed with different types of urgencies such as delayable or eager, that are modeled by several urgency variants of the timed automata model. However, most model checkers do not support such urgency semantics, except for the IF toolset that model checks timed automata with urgency against observers. This work proposes an Urgent Timed Automata (UTA) model with zone-based urgency semantics that gives the same model checking results as absolute urgency semantics of other existing urgency variants of the timed automata model, including timed automata with deadlines and timed automata with urgent transitions. A necessary and sufficient condition, called complete urgency, is formulated and proved for avoiding zone partitioning so that the system state graphs are simpler and model checking is faster. A novel zone capping method is proposed that is time-reactive, preserves complete urgency, satisfies all deadlines, and does not need zone partitioning. The proposed verification methods were implemented in the SGM CTL model checker and applied to real-time and embedded systems. Several experiments, comparing the state space sizes produced by SGM with that by the IF toolset, show that SGM produces much smaller state-spaces. ? 2009 Elsevier Inc. All rights reserved.
關聯:	Journal of Systems and Software 82 (10) , pp. 1627-1641
顯示於類別:	[資訊工程學系所] 期刊論文

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