This paper presents a high-performance architecture of a piecewise linear convolution interpolation for digital image. The kernel of the proposed method is built up of piecewise linear polynomial and approximates the ideal sinc-function in interval [-2, 2]. The proposed architecture reduces the computational complexity of generating weighting coefficients and provides a simple hardware architecture design, low computation cost and is easy to meet real-time requirement. The architecture is implemented on the Virtex-II FPGA, and the VLSI architecture has been successfully designed and implemented with TSMC 0.13μm standard cell library. The simulation results indicate that the interpolation quality of the proposed architecture is better than cubic convolution interpolations mostly, which is able to process various-ratio image scaling for HDTV in real-time. ?2010 IEEE.
Relation:
Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics 2010, Article number5641886, Pages 3632-3637
