An efficient architecture of extended linear interpolation for image processing

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Please use this identifier to cite or link to this item: http://140.128.103.80:8080/handle/310901/22783

Title:	An efficient architecture of extended linear interpolation for image processing
Authors:	Lin, C.-C.a, Sheu, M.-H.b, Chiang, H.-K.b, Liaw, C.a, Wu, Z.-C.c, Tsai, W.-K.b
Contributors:	Department of Computer Science, Tunghai University
Keywords:	Bi-cubic convolution;Image reconstruction;Interpolation;Scaling;VLSI
Date:	2010
Issue Date:	2013-05-21T09:16:41Z (UTC)
Abstract:	This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13 μm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 2S980 gates in a 450 χ 450μm2 chip is able to process digital image scaling for HDTV in real-time.
Relation:	Journal of Information Science and Engineering Volume 26, Issue 2, March 2010, Pages 631-648
Appears in Collections:	[資訊工程學系所] 期刊論文

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