A high gain, low noise wlan receiver for dual if double downconversion application in 90-nm RF CMOS

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Title:	A high gain, low noise wlan receiver for dual if double downconversion application in 90-nm RF CMOS
Authors:	Chang C.-P., Hou J.-A., Su J., Chen J.-H., Chen C.-W., Liou T.-S., Wong S.-C., Wang Y.-H.
Contributors:	Department of Electrical Engineering, Institute of Microelectronics, National Cheng-Kung University, Tainan, 701, Taiwan;RichWave Technology Corporation, Taipei 114, Taiwan
Keywords:	A high power gain, low noise WLAN receiver, using a 158 GHz fT 90-nm RF CMOS technology for dual IF double downconversion system-in-package application is demonstrated. The proposed circuit could improve the design flexibility of back-end stages due to its high power gain and low noise performances. The LNA and Mixer are biased at 1 V with 12.9 mA and 1.8 V with 5.5 mA, respectively. The proposed circuit delivers the double-sideband noise figure of 2.68 dB, conversion gain of 36.24 dB, IIP3 of -25 dBm, IIP2 of 21.1 dBm, and LO-IF isolation of -56.2 dB under the 1 dBm LO power, while maintaining the RF port and IF port return losses below -12.9 and -18.7 dB, respectively. ? 2007 Wiley Periodicals, Inc.
Date:	2007
Issue Date:	2013-06-24T09:05:55Z (UTC)
Relation:	Microwave and Optical Technology Letters 49(10)
Appears in Collections:	[工業工程與經營資訊學系所] 期刊論文

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