Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure

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Please use this identifier to cite or link to this item: http://140.128.103.80:8080/handle/310901/24963

Title:	Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure
Authors:	Huang, C.-H.;Huang, T.-Y.;Yang, C.-Y.;Chu, H.-P.;Lo, K.-H.;Hung, C.-Y.;Chang, K.-C.;Su, H.-D.;Huang, C.-F.;Gong, J.
Contributors:	Department of Electrical Engineering, Tunghai University
Keywords:	CMOS integrated circuits;MOSFET devices;Three dimensional;3-d profiles;CMOS technology;Drain MOSFETs;Fish bones;High voltage;Lateral MOSFETs;LDMOSFET;Low-voltage;MOS devices
Date:	2013-05-26
Issue Date:	2014-06-20T02:30:20Z (UTC)
Publisher:	Kanazawa
Abstract:	In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively. ? 2013 IEEE.
Relation:	2013 25th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2013 Proceedings of the International Symposium on Power Semiconductor Devices and Ics,P.249-252
Appears in Collections:	[電機工程學系所] 會議論文

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