This paper presents an efficient VLSI design of bicubic convolution interpolation for digital image processing. The architecture of reducing the computational complexity of generating coefficients as well as decreasing number of memory access times is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Based on our technique, the high-speed VLSI architecture has been successfully designed and implemented with TSMC 0.13?m standard cell library. The simulation results demonstrate that the high performance architecture of bi-cubic convolution interpolation at 279MHz with 30643 gates in a 498 x 498?m2 chip is able to process digital image scaling for HDTV in real-time. ?2008 IEEE.
Relation:
Proceedings - IEEE International Symposium on Circuits and Systems 2008, Article number4541459, Pages 480-483
