This paper presents a low-cost and high-speed architecture of bicubic convolution interpolation for high-quality digital image scaling. This architecture reduces the computational complexity of generating weighting coefficients and number of memory access times. Furthermore, it attempts to minimize the error propagation that results from the fraction truncations when calculating pixel coordinates under fixed-point operations. Error propagation significantly diminishes the output image quality for hardware interpolation. In order to avoid the inaccuracy accumulation, a simple periodical compensation technique is presented to improve the average root-mean-square error significantly. From the perspective of hardware cost, the presented architecture has ∼50% saving compared to the latest bi-cubic hardware design work. Finally, this architecture has been successfully designed and implemented with Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 /?m complimentary metal oxide semiconductor technology. The simulation results demonstrate that the high-performance architecture of bicubic convolution interpolation at 279 MHz with 30643 gates in a 498 X 498 pm chip is able to process various-ratio image scaling for full high-definition display device in real time. ?2008 SPIE and IS&T.
