目前實驗室新架設電漿化學氣相沉積系統，此系統會因為製程產生的粉塵堆積於氣導流板造成短路導致電漿狀態不穩定的情況，而在我們設計並改良後為了瞭解此系統合成矽奈米線之影響因素，因此針對電漿功率、製程壓力與觸媒厚度進行測試，結果顯示矽奈米線長度會隨著壓力或者電漿功率提高而增加，但是也會造成側向沉積使得矽奈米線直徑增加；而觸媒厚度增加雖然會使直徑增加，但並非側向沉積所造成，此外觸媒厚度與矽奈米線長度沒有直接關係。為了增加製程效率與減少大氣對樣品所造成的汙染，並且解決矽奈米在進行不同結構堆疊所遇到薄膜沉積不均勻的問題，因此我們設計並建構樣品傳輸裝置與原子層沉積系統，並與電漿化學氣相沉積系統結合，希望透過臨場製程解決此問題。我們最後成功利用原子層沉積系統於矽奈米線表面沉積等向均勻的氧化鋅薄膜，形成氧化鋅包覆矽奈米線異質結構。 The results of setting up new plasma chemical vapor deposition system (PECVD) in ours laboratory (LAMPS), this system would produce powder dust in syntheizing silicon nanowires process, and powder was piled up the shower hat. It wasn’t only caused short circuit but let plasma instable. Thus, we must to what is the influence factors of grew up the silicon nanowires in the new system after improving the problem. We were aimed at RF-power, pressure, and the thickness of catalyst for the measurement. The length of silicon nanowires would increase as the high synthesis pressure or high power, and the diameter of silicon nanowire increased in lateral deposition. Although the thickness of catalyst increased would caused diameter of silicon nanowire be raising , it doesn’t cause in lateral deposition. Therefore, the thickness of catalyst wasn’t the direct relation.For synthesizing the efficiency and decreasing the pollution of sample which be caused in air, we construct and design a new set of atomic layer deposition (ALD) and load-lock system that to integrate the PECVD system, and to solve the problem of thickness of thin film wasn’t uniform in atom structure different stacking. Finally we succeeded of pevious ALD system to the coaxial ZnO/Si heterostructure nanowires.
